1. Technical Field
The present invention relates to a multilayer wiring substrate, a semiconductor package, and a method of manufacturing the semiconductor package.
2. Related Art
Recently, a multilayer wiring substrate with a multilayered wiring layer has been used along with miniaturization of electronic parts. The multilayer wiring substrate is formed by sticking insulating layers which have wiring layers on the upper and the lower surfaces, on and under a core layer which is constituted by an insulating material and is located between the insulating layers.
According to the configuration described in Japanese Laid-open patent publication NO. H10-294560, the thickness of an insulating layer on which a higher ratio of the wiring portions of the wiring layers is formed is increased in comparison with those of other layers in order to control the warp of a substrate which is caused by density differences among wiring portions on a wiring layer.
In Japanese Laid-open patent publication NO. 2004-281924, there has been described a configuration in which two insulating layers with different physical properties are alternately laminated in order to reduce contraction along the surface to reduce deformations.
In Japanese Laid-open patent publication 2005-38906, there has been described a coreless thin-type wiring substrate with a thickness of equal to or less than 0.5 mm. In the board, a warp amount is made below a predetermined value or less by setting a stress of an insulating material in the outermost layer within a predetermined range.
By the way, a semiconductor package is formed by installing a semiconductor chip on a substrate, and by sealing the chip with a sealing resin. As the thickness of a sealing resin is usually very thick in comparison with that of a substrate and that of a semiconductor chip, the warp of the semiconductor package can be controlled by controlling the sealing resin. In such the case, the warp of the semiconductor package was not a problem. However, the thickness of the sealing resin has become thinner along with recent finer processing. Thereby, there has been caused a problem that, even if there is no warp in the substrate, there is caused a warp in the semiconductor package according to characteristics of the sealing resin, the semiconductor chip, and the substrate, when these components are built into a semiconductor package.
As described later, the semiconductor package is installed into a motherboard through a solder ball or the like, or is laminated on another semiconductor packages. Such building is usually performed under a high temperature. At that time, the building cannot be sometimes performed because the contraction rates and the extension rates of the components are largely different from each other according to characteristics of components and a warp is caused in the semiconductor package.
However, only reduction in the warp of a substrate has received attention, and the warp of a semiconductor package has not been able to be reduced in techniques described in Japanese Laid-open patent publication NOs. H10-294560, 2004-281924, 2005-38906.